1. Field of the Invention
Embodiments of the invention relate to a non-volatile memory device and an associated programming method. More particularly, embodiments of the invention relate to a non-volatile memory device and an associated programming method to prevent noise produced by a power voltage to improve the reliability of a cache program operation.
2. Discussion of Related Art
Flash memories are non-volatile memory devices that electrically store, read and delete data. These devices combine lower power consumption and fast access times as compared to a typical hard disk drive. A flash memory may be classified as a NOR or a NAND memory depending on the connection state of a cell transistor and a bit line. In a NOR type flash memory, two or more cell transistors are connected to one bit line in parallel. Data is stored by using the channel hot electron method and data is deleted by using the Fowler-Nordheim (F-N) tunneling method. In a NAND type flash memory, two or more cell transistors are connected to one bit line in series and data is stored or deleted by using the F-N tunneling method. Conventionally, the NOR type flash memory has a high current consumption. This makes it hard to achieve high-integration, but does accommodate high speed performance. NAND type flash memory devices utilize lower cell currents as compared to NOR type flash memory devices, and thus high-integration is easier to achieve.
FIG. 1A is a circuit diagram of a memory cell included in a conventional NAND type flash memory that includes word lines WL11 through WL14 and memory cells M11 through M14. Memory cells M11 through M14 form a string structure with transistors ST1 and ST2 which are connected between bit line BL and ground voltage VSS in series. Since the conventional NAND type flash memory uses a low cell current, programming of all memory cells connected to one word line is performed in programming operation 1. FIG. 1B is a circuit diagram of a memory cell included in a conventional NOR type flash memory including memory cells M21 through M26 connected between bit lines BL1 and BL2 and source lines CSL. In conventional NOR type flash memory, current consumption is significantly increased and thus, a programming operation of a fixed number of memory cells is performed in programming operation 1.
FIG. 2 is a timing diagram illustrating a cache program operation performed in a conventional non-volatile memory device. In the cache program operation, data that is to be programmed is input through a cache register. Data in the cache register is moved to a main register and then data stored in the main register is programmed to a memory cell array. As illustrated in FIG. 2, a data load command, an address, data input, and a cache program command are input through an input/output (I/O) port from an external controller. When the data load command is input, the cache register included in the conventional non-volatile memory device is cleared. As data is input through the I/O port, the data is loaded into the cache register. Also, the cache program command is input and a ready/busy (R/nB) signal and an internal ready/busy (Int.R/nB) signal are changed to a logic low in response to the cache program command. While the ready/busy (R/nB) signal is at a logic low, the data stored in the cache register is moved to the main register. While the data stored in the main register is programmed to the memory cell array, the ready/busy (R/nB) signal returns to a logic high. The external controller provides the data load command, an address of a page that is to be programmed, and data to the conventional non-volatile memory device. As the data load command is input, the conventional non-volatile memory device clears the cache register in which previous data was stored. If the cache register is not cleared, data input for a previous programming page may remain in the cache register and thus unintended programming may occur while programming a subsequent page.
The data load command may be input anytime during programming for the previous page, and thus, a clearing operation of the cache register can be performed in the middle of the previous page programming. However, in a specific section or period during cache programming (for example, a section of sensing data for verifying a programming operation), reliability of the operation may be significantly decreased due to power voltage noise. When a clearing operation of the cache register occurs in the exemplary sensing section described above, a portion of data of the register is simultaneously changed. Consequently, noise associated with the power voltage may be generated, thereby decreasing the reliability of the programming operation. While performing a cache program operation, the effects of power voltage noise cannot be removed. This decreases the reliability of the cache program operation.